Complementary Metal-Oxide Semiconductor (CMOS) has been the semiconductor technology of choice since the late 1970's, and in 1998 the 0.25 micron CMOS technology generation is in production. There are many reasons to choose CMOS over other technologies. The most important is the reduced power consumption, because the basic building block of circuits for binary logic, the CMOS “Inverter”, only consumes power when changing logic states.
The fundamental factors determining the performance of standard “Planar Technology” are the channel length of the MOSFETs, and the parasitic capacitances. For deep sub-micron CMOS, as the gate lengths get shorter, leakage current tends to get higher, and the overall process technology becomes more complex. Not only the number of processing steps increases, but the complexity and difficulty of some of those steps is also increased. Since to make CMOS circuits, NMOS and PMOS devices are needed, many Front-End processing steps have to be made twice, separately for each device type.
However, CMOS circuits can also be made with other MOSFET architectures, such as Vertical MOSFETs (see reference [1]). The perspectives opened by Vertical MOSFETs are very attractive. That is especially true when considering the technological and fundamental physical limitations facing conventional (Planar) MOSFETs for gate lengths below 100 nm. For Vertical MOSFETs the channel length is defined by the doping and/or heterojunction profiles, made by low temperature epitaxy. Lithography defines the cross section of the devices (channel width), and therefore the density of integration.
The present invention pertains to the field of Complementary Metal-Insulator-Semiconductor Field-Effect Transistors (C-MISFETs). Since the most common insulator is an oxide (silicon dioxide), these devices are almost always designated by Complementary Metal-Oxide-Semiconductor Field-Effect Transistors (C-MOSFETs). More specifically, it pertains to CMOS circuits made with a new kind of Vertical MOSFETs.
The present invention, introduces a MOSFET device that behaves as N- or P-type transistor, depending only on the applied bias. Setting of the source voltage supply, determines if the device will behave as a NMOS or as a PMOS. For positive drain to source (VDS) and gate to source (VGS) voltages, the device behaves as NMOS. For negative drain to source (VDS) and gate to source (VGS) voltages, the same device acts like a PMOS. Therefore, with the device of the present invention it is possible to make complementary circuits (CMOS), even though only a single device type is fabricated, which “a priori” is neither N- or P-type.
The subject of this invention will hereafter be designated by “Single Device Complementary Metal Oxide Semiconductor Field Effect Transistor”, or SD-CMOS.
The independence of channel length from lithography, and the kind of doping and/or heterojunction profiles possible with low temperature epitaxy, enables the fabrication of Vertical MOSFETs with channels only tens of nanometers long, and with atomic layer control across the entire wafer. The limitations to make Vertical MOSFETs with very short channel lengths will no longer be technological, but related to device physics.
Vertical MOSFETs have an intrinsic advantage over horizontal MOSFETs: it is straightforward to build an asymmetry of the source to channel junction, versus the channel to drain junction. With horizontal MOSFETs, it is also possible to introduce asymmetry, but that comes at a cost in terms of process complexity (extra masks to differentiate source from drain for each type of device). And in any case, the doping and/or heterojunction profiles (made by ion implantation) can never come close to what low temperature epitaxy has demonstrated.
Like with Horizontal homojunction MOSFETs, Vertical homojunction MOSFETs suffer from Short Channel Effect (SCE), albeit at shorter channel lengths due to the ability to have sharper doping profiles, and therefore reduced depletion widths. Numerical simulations of a “Planar-Doped” Vertical MOSFET with a 50 nm channel length, predict very high performance levels (see reference [2]). But as channel length is further reduced, higher doping levels are needed to keep the electrostatic barrier between source and channel. In the limit, even without any bias (at the drain or gate), the built-in electric field, induces band to band tunneling through the source to channel barrier. Naturally, the necessity of applying drain bias, leads to even stronger scaling limitations due to Drain Induced Barrier Lowering (DIBL). For these reasons, it has been predicted (see reference [1]), that due to SCE and DIBL, the practical limit for how short channels can be, is around 80 nm.
An alternative type of Vertical MOSFETs, the Vertical Heterojunction MOSFETs (VH-MOSFETs), uses heterojunctions instead of homojunctions to build the source to channel electrostatic barrier (see reference [3]). Because the potential barrier is originated by a heterojunction, there is no need to introduce doping in the channel to make the barrier, and therefore the device is, by definition “fully depleted”. Also the heterojunction barrier exists across the entire channel thickness, and therefore removes any restriction on the distance between gates. With this device architecture, simulations show that ultra-short channels are possible (down to 10 nm), without suffering from SCE or DIBL (see reference [3]). The device type (NMOS or PMOS) is defined by what type of dopant is incorporated in the source and drain regions.
Numerical simulations of Double-Gate SOI CMOS with 30 nm gate/channel lengths (see reference [4]), predict extraordinary performance levels. A very illustrative parameter is the CMOS ring oscillator delay being less than 1 picosecond. Equal or better performance levels should be expected for the VH-MOSFET with channel lengths like 20 nm for example.
CMOS integration schemes have been proposed (see reference [3]), where the device layers of one device type are stacked on the device layers of the other device type, thereby enabling a single epitaxial growth step, and a common gate stack (gate insulator and gate electrode). Such integration schemes offer the perspective of significant overall front-end process simplification, and area gains, over configurations where NMOS and PMOS transistors would be made “side by side”.
Vertical MOSFETs have yet other attractive features. It has been shown how Vertical MOSFETs make possible memory cells, with a quarter of the area of cells made with planar MOSFETs, for the same generation of lithography equipment (see references [5, 6, 7]). For decades, DRAM has driven the progress in process technology. When optical lithography finds its ultimate limitations (believed to be around 100 nm), it is very likely that cells made with Vertical MOSFETs will be seriously considered as viable alternatives to increase the bit density.
However, and assuming that the capability of making Vertical MOSFETs with very short channels is to be fully exploited, it is required to have very low temperature processing (typically, below the temperature at which dopants will start to significantly diffuse and/or strained layers relax). Vertical MOSFETs, regardless of their channel length and particular device layer composition/profile, different device regions like gate, have source and drain lying on different planes. Therefore contacts to these regions (and to gate electrode) must be made by separate sequences of contact hole formation and contact hole filling with a metal.
Recently there has been renewed interest in the use of germanium as the semiconductor material for the fabrication of Complementary Metal-Oxide-Semiconductor (CMOS) devices and circuits [19, 20, 21]. This renewed interest was sparked by the realization that the conventional methods of improving the performance of CMOS devices and circuits are fast approaching insurmountable barriers. These barriers are the scaling limits of silicon-based CMOS, now thought to be at 20 nm gate lengths, using gate insulators with high dielectric constant, also known as “high-k dielectrics”, and metal gate electrodes.
It is perceived that in order to increase performance, it is necessary to switch from silicon to germanium, which is very attractive due to its much higher electron mobility (3900 cm2V-1s-1 versus 1500 cm2V-1s-1) and hole mobility (1900 cm2V-1s-1 versus 450 cm2V-1s-1). Germanium is also very attractive due to being a very well known material, in fact used for microelectronics applications before silicon became the material of choice, and to its seamless integration in conventional silicon CMOS processing, as proven by the now widely deployed Silicon-Germanium BiCMOS process technology. Furthermore, some of the technological difficulties faced by silicon-based CMOS for scaling to the 20 nm gate length generation may be easier to overcome with germanium-based CMOS.
One of these difficulties is to achieve and maintain a silicon surface free of the native oxide, with low temperature processing only. This inherent characteristic of silicon was quite useful while silicon-oxide was the gate insulator of choice. It has always been one of the major problems that must to be solved in order to perform epitaxial deposition of silicon-related alloys and/or superlattices, such as silicon-germanium (Sil-xGex), silicon-carbon (Sil-yCy), silicon-germanium-carbon (Sil-x-yGexCy), etc. This has also been a problem for other epitaxially compatible materials such as insulators and conductors. Examples of these materials are: CaF2, CdF2, AlN, Al2O3, CeO2, SrRuO3, BaRuO3, TiN, etc.
Since the times before silicon became the material of choice for CMOS, it has been known that the native germanium-oxide is not stable and can be simply rinsed away. Also, germanium melts at a much lower temperature than silicon (937° C. versus 1415° C.), the electrical activation of ion-implanted dopant species takes place at much lower temperatures (400° C. versus the typical 900° C.), epitaxial growth can also be done at much lower temperatures (300° C. versus the typical 650° C.), formation of metal-germanides takes place at significant lower temperatures than metal-silicides, etc. The overall ability to perform the most critical steps of CMOS processing at much lower temperatures than silicon, enables the incorporation of other materials that presently cannot be integrated during CMOS processing. This opens a new field in monolithic integration with very large potential for added functionality at low cost.
The benefits of a straightforward very low temperature surface preparation suitable for epitaxy of Germanium-based alloys and/or superlattices of for example Gel-xSix, Gel-ySny, Gel-x-ySixSny, and non Germanium-based materials such as BaTiO3 [22], can bring radical changes to device processing and overall CMOS process flow. One of the limitations to fabricating multiple epitaxial devices on silicon substrates, each requiring its separate surface cleaning and layer deposition, is the fact that the high temperature annealing needed to insure good epitaxial growth on the silicon surface, disrupts the “as deposited” heterojunction and doping profiles that had been formed for the previous epitaxial device.
A substrate material that allows good epitaxial growth on surfaces pre-cleaned and/or annealed at very low temperature, enables process flows consisting of multiple sequential epitaxial deposition steps, that can be used to fabricate different devices and/or different portions of a single device, without any impact to any previous heterojunction and/or doping profiles that may already exist on that substrate. This capability is a key element to fabricate multiple epitaxial layers, belonging to one or more devices, having atomically sharp interfaces between homojunctions and/or heterojunctions, and to preserve compositional and/or impurity gradients inside such layers.
In conclusion, switching the CMOS semiconductor material from silicon to germanium substrates brings the following advantages: higher electron mobility, higher hole mobility, very low temperature for annealing ion-implanted doping impurities, and straightforward preparation of surfaces free from native-oxide. This last point has extraordinary benefits for very low temperature surface preparation before epitaxy (selective or non-selective), direct interface between germanium surface and high-k gate insulator, formation of metal-germanides (for Schottky or Ohmic contacts), and for process flows with multiple epitaxial deposition steps.